Various conventional techniques exist for saving power in processing cores. One such example is clock gating, which may include turning a clock signal on and off to specific circuitry. When that circuitry is no longer receiving a clock signal, it stops processing and transferring information, thereby reducing its dynamic power consumption to zero or very near zero. However, the various transistors of the circuitry may leak current even while the clock signal is gated. In some conventional circuits, leakage current may be responsible for a significant percentage of overall power consumed. In fact, as transistors continue to get smaller, leakage power may become more significant in some systems.
Another conventional technique for saving power in processing cores includes power collapsing. Power collapsing may include reducing an operating voltage of a circuit to zero, for example, by use of a switch that disconnects the circuit from power when the circuit is not needed. Later on, when the system expects to use the circuit, the system can restore power by closing a switch to connect the circuit to power. Such conventional techniques may provide acceptable reductions in leakage power, but either erase state information or employ complicated systems to preserve the state information during power down. Erasing state information may cause unacceptable latency, and complicated systems to preserve state information may actually consume more power than can be saved through power collapsing. There is therefore a need for improved clocking and gating techniques.
Other techniques include powering different portions of a system separately. In one example, Static Random Access Memory (SRAM) is powered separately from processing logic circuits. In such systems, the SRAM includes megabytes or gigabytes of storage capacity, and also is optimized to be efficient by utilizing specific voltage ranges for storing data. Such conventional techniques arise because large blocks of SRAM have different operational requirements than their corresponding processing logic circuits and, thus, can be treated differently. While it is possible to use power gating separately on processing logic circuits and on large blocks of SRAM, there is currently no technique that treats circuits within the processing logic separately from other circuits within the processing logic.